Publications associées à Conception assistée par ordinateur pour l'électronique

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Graph generative deep learning models with an application to circuit topologies

Igor Krawczuk

Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison. Managing their complexity and facilitating their design drove part of the co-evolution of mode ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Strategy to systematically design and deploy the ITER plasma control system: A system engineering and model-based design approach

Federico Alberto Alfredo Felici, Richard Pitts, Federico Pesamosca, Anna Ngoc Minh Trang Vu

The paper details the process of developing the ITER Plasma Control System (PCS), that is, how to design and deploy it systematically, in the most efficient and effective manner. The integrated nature of the ITER PCS, with its multitude of coupled control ...

Elsevier Science Sa2024

A Dual-Channel Gate Driver Design with Active Voltage Balancing Circuit for Series Connection of SiC MOSFETs

Drazen Dujic

Dual-channel gate driver is commonly utilized in the industry for accommodating the widespread use of half-bridge power modules. As wide-bandgap devices become increasingly prevalent due to their superior switching characteristics compared with conventiona ...

2024

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

The Digital Ethics Canvas: A Guide For Ethical Risk Assessment And Mitigation In The Digital Domain

Patrick Jermann, Cécile Hardebolle, Vladimir Macko, Adrian Christian Holzer, Vivek Ramachandran

Ethical concerns in the digital domain are growing with the extremely fast evolution of technology and the increasing scale at which software is deployed, potentially affecting our societies globally. It is crucial that engineers evaluate more systematical ...

2023

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

Qian Wang, Simone Scarfì, Varun Sharma, Konstantin Androsov, Xin Chen, Rakesh Chawla, Tian Cheng, Werner Lustermann, Andromachi Tsirou, Andrea Rizzi, Jessica Prisciandaro, David Vannerom, Davide Di Croce, Albert Perez, Alessandro Caratelli, François Robert, Davide Ceresa, Chun Xia, Yong Yang, Ajay Kumar, Ashish Sharma, Georgios Anagnostou, Muhammad Ahmad, Francesco Fiori, Kai Yi, Jing Li, Hui Wang, Stefano Michelis, François Bianchi, David Parker

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor sta ...

2022

Cost-Based Decision Support System: A Dynamic Cost Estimation of Key Performance Indicators in Manufacturing

Dimitrios Kyritsis, Foivos Psarommatis Giannakopoulos

An attempt is made to translate five generic key performance indicators (KPIs) into a continuous real-time cost function in a batch order-based manufacturing environment. The challenge of controlling and optimizing resource utilization, production efficien ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications

Matthias Neuenschwander

The field of micro electromechanical systems (MEMS) evolved from the microelectronic industry and the technologies developed to fabricate integrated circuits. As a result, MEMS are commonly fabricated on silicon wafers. The development of MEMS has been dri ...

EPFL2022

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Giovanni De Micheli, Heinz Riener, Alessandro Tempia Calvino, Shubham Rai, Akash Kumar

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

2022

Revisiting the Impact of Morphology and Oxidation State of Cu on CO2 Reduction Using Electrochemical Flow Cell

Michael Graetzel, Shaik Mohammed Zakeeruddin, Jing Gao, Dan Ren

Electroreduction of carbon dioxide (CO2) in a flow electrolyzer represents a promising carbon-neutral technology with efficient production of valuable chemicals. In this work, the catalytic performance of polycrystalline copper (Cu), Cu2O-derived copper (O ...

AMER CHEMICAL SOC2022

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Reconfigurable Drone System for Transportation of Parcels With Variable Mass and Size

Dario Floreano, Fabrizio Schiano, Przemyslaw Mariusz Kornatowski, Leonardo Cencetti

Cargo drones are designed to carry payloads with predefined shape, size, and/or mass. This lack of flexibility requires a fleet of diverse drones tailored to specific cargo dimensions. Here we propose a new reconfigurable drone based on a modular design th ...

2022

Integrated electronic device with embedded microchannels and a method for producing thereof

Elison de Nazareth Matioli, Remco Franciscus Peter van Erp

The present invention relates to a method for fabricating an integrated electronic device with a microchannel, comprising the steps of: - Providing a homogeneous or heterogeneous substrate with one or more layers of material, respectively; - Forming at lea ...

2021

LUT-Based Optimization For ASIC Design Flow

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

2021