Instruction-level parallelism

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Publications associées (31)

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon, Marco Antonio Rios

With the spread of cloud services and Internet of Things concept, there is a popularization of machine learning and artificial intelligence based analytics in our everyday life. However, an efficient deployment of these data-intensive services requires per ...

2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

Asynchronous Simulation of Neuronal Activity

Bruno Ricardo Da Cunha Magalhães

Simulations of the electrical activity of networks of morphologically-detailed neuron models allow for a better understanding of the brain. Short time to solution is critical in order to study long biological processes such as synaptic plasticity and learn ...

EPFL2019

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Manolis Karpathiotakis, Raja Appuswamy, Periklis Chrysogelos

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

Fully-Asynchronous Cache-Efficient Simulation of Detailed Neural Networks

Felix Schürmann, Michael Lee Hines

Modern asynchronous runtime systems allow the re-thinking of large-scale scientific applications. With the example of a simulator of morphologically detailed neural networks, we show how detaching from the commonly used bulk-synchronous parallel (BSP) exec ...

SPRINGER INTERNATIONAL PUBLISHING AG2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Manolis Karpathiotakis, Raja Appuswamy, Periklis Chrysogelos, Panagiotis Sioulas

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

Mitsuba 2: A Retargetable Forward and Inverse Renderer

Wenzel Alban Jakob, Tizian Lucien Zeltner, Delio Aleardo Vicini, Merlin Eléazar Nimier-David

Modern rendering systems are confronted with a dauntingly large and growing set of requirements: in their pursuit of realism, physically based techniques must increasingly account for intricate properties of light, such as its spectral composition or polar ...

ASSOC COMPUTING MACHINERY2019

Fast Energy Estimation Through Partial Execution of HPC Applications

Marina Zapater Sancho, José Luis Ayala Rodrigo

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via d ...

IEEE2018

Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins

Anastasia Ailamaki, Georgios Psaropoulos

Index joins present a case of pointer-chasing code that causes data cache misses. In principle, we can hide these cache misses by overlapping them with computation: The lookups involved in an index join are parallel tasks whose execution can be interleaved ...

2019

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

IEEE2018

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Marco Mattavelli, Malgorzata Maria Michalska, Simone Casale Brunet, Endri Bezati

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given opt ...

2017

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