Publications associées à Intel P6

Rebooting Virtual Memory with Midgard

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Periklis Chrysogelos

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

2023

Boosting Efficiency of External Pipelines by Blurring Application Boundaries

Anastasia Ailamaki, Anna Patricia Herlihy, Periklis Chrysogelos

Modern application development addresses increasingly specialized problems using domain-specific utilities, such as Optical Code Recognition and standalone statistical tools. The diversity of tooling, combined with the ever-growing volume of data, requires ...

2022

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Adaptive Cache Mode Selection for Queries over Raw Data

Anastasia Ailamaki, Tahir Azim, Azqa Nadeem

Caching the results of intermediate query results for future re-use is a common technique for improving the performance of analytics over raw data sources. An important design choice in this regard is whether to lazily cache only the offsets of satisfying ...

2018

Quantitative phase imaging in biomedicine

Christian Depeursinge

Quantitative phase imaging (QPI) has emerged as a valuable method for investigating cells and tissues. QPI operates on unlabelled specimens and, as such, is complementary to established fluorescence microscopy, exhibiting lower phototoxicity and no photobl ...

Nature Publishing Group2018

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Marco Mattavelli, Endri Bezati, Anatoly Prihozhy, Ab Al Hadi Bin Ab Rahman

This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are th ...

Ieee-Inst Electrical Electronics Engineers Inc2015

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman, Mohammad Alisafaee, Yusuf Onur Koçberber, Stavros Volos, Ilknur Cansu Kaynak, Adrian Daniel Popescu, Al Mutaz Adileh, Dorde Jevdic

Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and calling for improvements in the computational ...

Association for Computing Machinery2012

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010

Reliability-Aware Design for Nanometer-Scale Devices

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, José Luis Ayala Rodrigo

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expecte ...

2008

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

David Atienza Alonso, Pablo Garcia del Valle, José Luis Ayala Rodrigo

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be ...

IEEE Computer Society2008

Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

VSH, an efficient and provable collision-resistant hash function

Arjen Lenstra

We introduce VSH, very smooth hash, a new S-bit hash function that is provably collision-resistant assuming the hardness of finding nontrivial modular square roots of very smooth numbers modulo an S-bit composite. By very smooth, we mean that the smoothnes ...

Springer Verlag2006