Publications associées à Intel HD Graphics

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Malware in the SGX supply chain: Be careful when signing enclaves!

Rafael Pereira Pires, Pascal Felber

Malware attacks are a significant part of the new software security threats detected each year. Intel Software Guard Extensions (SGX) are a set of hardware instructions introduced by Intel in their recent lines of processors that are intended to provide a ...

2022

High Performance Computing for gravitational lens modeling: Single vs double precision on GPUs and CPUs

Jean-Paul Richard Kneib, Markus Rexroth, Christoph Ernst René Schäfer

Strong gravitational lensing is a powerful probe of cosmology and the dark matter distribution. Efficient lensing software is already a necessity to fully use its potential and the performance demands will only increase with the upcoming generation of tele ...

ELSEVIER2020

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

David Atienza Alonso, Marina Zapater Sancho, Arman Iranfar, Luis Maria Costero Valero

The advent of online video streaming services along with the users' demand for high-quality contents require High Efficiency Video Coding (HEVC), which provides higher quality and compression at the cost of increased complexity. On one hand, HEVC exposes a ...

2020

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

James Gonzalo King, Felix Schürmann, Michael Lee Hines, Fabien Jonathan Delalondre, Aleksandr Ovcharenko, Pramod Shivaji Kumbhar, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

Using the new VPMADD instructions for the new post quantum key encapsulation mechanism SIKE

Dusan Kostic

This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename "Cannon Lake"), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is ...

IEEE COMPUTER SOC2019

GPU-Accelerated Finite Volume Particle Simulation of Free Jet Deviation by Multi-jet Rotating Pelton Runner

Siamak Alimirzazadeh

Numerical simulation of Pelton turbine hydrodynamics is helpful to identify the energy loss mechanisms in the runner and minimize their effect. However, it is a challenging task that involves handling the unsteady free surface flow and moving boundaries re ...

EPFL2019

An Analytical Model of Hardware Transactional Memory

Willy Zwaenepoel, Paolo Romano, Diego Didona

This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in ...

2017

Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska, Junaid Jameel Ahmad

The exploration of different design configurations of dynamic dataflow programs executed on many-core or multi-core platforms is, in general, a very difficult task. Determining a close-to-optimal partitioning, scheduling and buffer dimensioning configurati ...

2017

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Theo Lasser, Paul James Marchand, Daniel Pawel Szlag, Marcin Antoni Sylwestrzak

We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Robert Granger, Philipp Svetolik Jovanovic

A popular approach to tweakable blockcipher design is via masking, where a certain primitive (a blockcipher or a permutation) is preceded and followed by an easy-to-compute tweak-dependent mask. In this work, we revisit the principle of masking. We do so a ...

Springer Int Publishing Ag2016

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Trach-Minh Tran, Claudio Gheller

We present a portable platform, called PIC_ENGINE, for accelerating Particle-In-Cell (PIC) codes on heterogeneous many-core architectures such as Graphic Processing Units (GPUs). The aim of this development is efficient simulations on future exascale syste ...

Elsevier Science Bv2016

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Christoph Studer

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and ...

IEEE2010