Concept

Serial Peripheral Interface

Publications associées (26)

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Catherine Lucie Jéromine Gasnier

Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a ...

2013

Modeling Stressed MOS Oxides Using a Multiphonon-Assisted Quantum Approach—Part I: Impedance Analysis

Alexandre Schmid, Yusuf Leblebici, Davide Garetto

Complementary MOS device electrical performances are considerably affected by the degradation of the oxide lay- ers and Si/SiO2 interfaces. A general expression for electrically stressed MOS impedance has been derived and applied within the nonradiative mu ...

Institute of Electrical and Electronics Engineers2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012

Power and pin efficient chip-to-chip communications with common-mode rejection and sso resilience

Mohammad Amin Shokrollahi, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality ...

2012

Monitoring and troubleshooting wireless sensor nodes by measuring the supply current waveform

Pierre-André Farine, Alexis Boegli, Mitko Tanevski

A troubleshooting method for debugging wireless sensor nodes using measurements of the supply current waveform and logic outputs is presented. The troubleshooting and debugging technique uses the supply current waveform in conjunction with the measurement ...

Elsevier Ltd.2010

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010