Publications associées à Hardware emulation

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Emulating Multimemristive Behavior of Silicon Nanowire-Based Biosensors by Using CMOS-Based Implementations

Sandro Carrara, Junrui Chen, Kapil Bhardwaj

The research presented in this article draws inspiration from previous efforts aimed at replicating the functions of various solid-state memristors using a variety of materials. The memristor circuit emulator serves as a cost-effective tool for circuit des ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Green Cryptography and Other Optimisations

Andrea Felice Caforio

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Harsh Ambarishkumar Shukla

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

EPFL2021

System-level Design of Adaptive Wearable Sensors for Health and Wellness Monitoring

Elisabetta De Giovanni

In recent years, population aging and the consequent higher incidence of noncommunicable diseases, have increased the need for long-term health monitoring. Moreover, as healthcare cost is projected to grow substantially by 2030 in OECD countries, the deman ...

EPFL2021

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Winston Jason Haaswijk

Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...

EPFL2019

SPADE: Tuning scale-out OLTP on modern RDMA clusters

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

Distributed transactions on modern RDMA clusters promise high throughput and low latency for scale-out workloads. As such, they can be particularly beneficial to large OLTP workloads, which require both. However, achieving good performance requires tuning ...

Association for Computing Machinery2018

Trading off Energy versus Accuracy in Modern Computing Systems : From Digital Circuit Design to Programming Techniques

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

Spatial: A Language and Compiler for Application Accelerators

Christos Kozyrakis, Yunqi Zhang

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for pr ...

ASSOC COMPUTING MACHINERY2018

Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning

Georgios Chatzopoulos

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

EPFL2018

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs offer high performance coupled with energy efficiency making them extremely attractive computational resources within a cloud ecosystem. However, to achieve this integration and make them easy to program, we first need to enable users with varying ex ...

2017

Electronic solutions for power system emulation

Guillaume Olivier Lanz

Nowadays electric power systems are subject to continuous changes and the needs in the power generation and delivery service are constantly increasing, with a higher complexity of a progressively more distributed network. Because the impact of a failure ca ...

EPFL2017

Efficient Hardware Design Of Iterative Stencil Loops

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Paolo Ienne, Andrew James Becker, Ryan Charles Kastner, Wei Hu

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...

Assoc Computing Machinery2016