Unité de calcul en virgule flottante

Applied sciences
Génie informatique
Matériel informatique
Microprocesseur

À propos
Confidentialité
Mentions légales

Graph Chatbot

Publications associées (27)

Mixed-precision architecture based on computational memory for training deep neural networks

Irem Boybat Kara, Evangelos Eleftheriou, Abu Sebastian

Deep neural networks (DNN) have revolutionized the field of machine learning by providing unprecedented human-like performance in solving many real-world problems such as image or speech recognition. Training of large DNNs, however, is a computationally in ...

IEEE2018

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch

Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Towards a Compiler for Reals

Viktor Kuncak, Eva Darulova

Numerical software, common in scientific computing or embedded systems, inevitably uses a finite-precision approximation of the real arithmetic in which most algorithms are designed. In many applications, the roundoff errors introduced by finite-precision ...

2017

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Ad ...

Ieee2016

A Low-power Carry Cut-Back Approximate Adder with Fixed-point Implementation and Floating-point Precision

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

This paper introduces an approximate adder architecture based on a digital quasi-feedback technique called Carry Cut-Back in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach preve ...

Ieee2016

A Bio-Inspired Reconfigurable Architecture for Local Binary Descriptors

Selman Ergünay, Yusuf Leblebici

Limited resources of embedded devices and increased real time constraints have raised interest to the binary description methods over the floating-point ones such as SIFT and SURF in computer vision applications. Although many software applications of the ...

Ieee2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Page 2 sur 2