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Publications associées (30)

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

Manycore Network Interfaces for In-Memory Rack-Scale Computing

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

Datacenter operators rely on low-cost, high-density technologies to maximize throughput for data-intensive services with tight tail latencies. In-memory rack-scale computing is emerging as a promising paradigm in scale-out datacenters capitalizing on commo ...

2015

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Subhasish Mitra

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

Assoc Computing Machinery2014

Making Wide-Issue VLIW Processors Viable on FPGAs

Paolo Ienne, Madhura Purnaprajna

Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors ...

2012

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

Closing the Gap between FPGA and ASIC : Balancing Flexibility and Efficiency

Hadi Parandeh Afshar

Despite many advantages of Field-Programmable Gate Arrays (FPGAs), they fail to take over the IC design market from Application-Specific Integrated Circuits (ASICs) for high-volume and even medium-volume applications, as FPGAs come with significant cost in ...

EPFL2012

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

Paolo Ienne, Ali Galip Bayrak, Nikola Velickovic, Wayne Burleson

Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leak ...

2012

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Richard Thavot, Ab Al Hadi Bin Ab Rahman

This paper presents some strategies for design space exploration of FPGA-based signal processing systems that are specified using the CAL dataflow language. The actor- oriented, high-level of abstraction provided by CAL allows flexible exploration and cons ...

2012

Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL

Marco Mattavelli, Anatoly Prihozhy, Ab Al Hadi Bin Ab Rahman

This paper describes a pipeline synthesis and optimization technique that increases data throughput of FPGA-based system using minimum pipeline resources. The technique is applied on \CAL dataflow language, and designed based on relations, matrices and gra ...

Hindawi Publishing Corporation2011

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