Publications associées à Circuits statiques et dynamiques

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

Alexandre Schmid, Keyvan Farhang Razi

A low-power digital charge balancing system, which ensures the safe operation of constant-current biphasic stimulation is presented. The concept of the proposed charge-balancing technique is to utilize a hybrid method consisting of anodic pulse modulation ...

IEEE2023

New ultrahigh-speed device concepts: from THz nanoplasma devices to glass-like electronics for neuromorphic computation

Mohammad Samizadeh Nikooytabalvandani

There is a never-ending push for electronic systems to provide faster operation speeds, higher energy efficiencies, and higher power capabilities at smaller scales. These requirements are apparent in different areas of electronics, from radiofrequency (RF) ...

EPFL2023

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications

Francesco Piro

Monolithic pixel sensors integrate the sensor matrix and readout in the same silicon die, and therefore present several advantages over the more largely used hybrid detectors in high-energy physics. They offer an easier detector assembly, lower cost, lower ...

EPFL2023

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

Marco Mattavelli, Catherine Dehollain, Diego Ruben Barrettino, Kerim Türe, Mustafa Besirli, Franco Maloberti

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly releva ...

2022

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic, Hossein Asadi, Zeinab Seifoori

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling ...

IEEE2021

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic, Hossein Asadi

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

Compact Circuits for Combined AES Encryption/Decryption

Subhadeep Banik

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cate ...

2019

Impact of Fin Width on Tri-Gate GaN MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Giovanni Santoruvo, Taifang Wang

In this paper, we present a detailed investigation of the impact of fin width (w(fin)) on tri-gate AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). As w(fin) is reduced, the threshold voltage (V-TH) increases, which is due ...

2019

Voltage References for the Ultra-Wide Temperature Range from 4.2 K to 300 K in 40-nm CMOS

Edoardo Charbon, Fabio Sebastiano

This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2 K to ...

IEEE2019

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Edoardo Charbon, Harald Arjan Robert Homulle

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires ...

2018

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu, Maciej Jerzy Ciesielski

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

Integrated ESOP Refactoring for Industrial Designs

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Winston Jason Haaswijk

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operat ...

IEEE2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Amongst 2-dimensional (2D) semiconductors of the transition-metal di-chalcogenide (TMDC) family [1], tungsten diselenide (WSe2) has shown ambipolar behavior [2], [3] coupled with high carrier mobility [4] and CMOS-like devices have been experimentally demo ...

IEEE2018

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread ...

2018