Publications associées à Hardware-assisted virtualization

CloudProphet: A Machine Learning-Based Performance Prediction for Public Clouds

David Atienza Alonso, Marina Zapater Sancho, Luis Maria Costero Valero, Darong Huang, Ali Pahlevan

Computing servers have played a key role in developing and processing emerging compute-intensive applications in recent years. Consolidating multiple virtual machines (VMs) inside one server to run various applications introduces severe competence for limi ...

2024

A RISC-V Extension to Minimize Privileges of Enclave Runtimes

Edouard Bugnion, Neelu Shivprakash Kalani

In confidential computing, the view of the system software is Manichean: the host operating system is untrusted and the TEE runtime system is fully trusted. However, the runtime system is often as complex as a full operating system, and thus is not free fr ...

ACM2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Alexandre Schmid, Lizeth Gonzalez Carabarin

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

IEEE2022

Design of a Collimation Section for the FCC-ee

Tatiana Pieloni, Bruce Roderik, Frank Zimmermann

The design parameters of the FCC-ee foresee operation with a total stored beam energy of about 20 MJ, exceeding those of previous lepton colliders by almost two orders of magnitude. Given the inherent damage potential, a halo collimation system is studied ...

JACoW Publishing2022

Performance Characterization of HTAP Workloads

Anastasia Ailamaki, Utku Sirin, Sandhya Dwarkadas

Hybrid Transactional and Analytical Processing (HTAP) systems have become popular in the past decade. HTAP systems allow running transactional and analytical processing workloads on the same data and hardware. As a result, they suffer from workload interfe ...

IEEE COMPUTER SOC2021

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

JIT works: decide when all data is known (VLDB Women in Database Research Award talk)

Anastasia Ailamaki

When the time comes to make a critical decision, it is of paramount importance to prepare enough so that all the information necessary is available at decision time. Under-preparation leads to uninformed decisions; over-preparation, however, may lead to co ...

ASSOC COMPUTING MACHINERY2020

Lupulus: A Flexible Hardware Accelerator For Neural Networks

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Robert Giterman, Andreas Toftegaard Kristensen

Neural networks have become indispensable for a wide range of applications, but they suffer from high computational- and memory-requirements, requiring optimizations from the algorithmic description of the network to the hardware implementation. Moreover, ...

IEEE2020

Micro-architectural Analysis of OLAP: Limitations and Opportunities

Anastasia Ailamaki, Utku Sirin

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, ...

ASSOC COMPUTING MACHINERY2020

NRStitcher: non-rigid stitching of terapixel-scale volumetric images

Anne Bonnin, Marco Stampanoni

A Summary: In modern microscopy, the field of view is often increased by obtaining an image mosaic, where multiple sub-images are taken side-by-side and combined post-acquisition. Mosaic imaging often leads to long imaging times that can increase the proba ...

2019

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers

David Atienza Alonso, Marina Zapater Sancho, Ali Pahlevan, Xiaoyu Qu

Modern cloud data centers (DCs) need to tackle efficiently the increasing demand for computing resources and address the energy efficiency challenge. Therefore, it is essential to develop resource provisioning policies that are aware of virtual machine (VM ...

2018

Distributed Optimization and Control using Operator Splitting Methods

Georgios Stathopoulos

The significant progress that has been made in recent years both in hardware implementations and in numerical computing has rendered real-time optimization-based control a viable option when it comes to advanced industrial applications. At the same time, t ...

EPFL2018

Decoder Partitioning: Towards Practical List Decoding of Polar Codes

Rüdiger Urbanke, Seyed Hamed Hassani, Marco Mondelli

Polar codes represent one of the major recent breakthroughs in coding theory and, because of their attractive features, they have been selected for the incoming SG standard. As such, a lot of attention has been devoted to the development of decoding algori ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Pascal Giard

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been ...

Ieee2017

The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplan

Edouard Bugnion, Christos Kozyrakis, Georgios Prekas, Mia Primorac, Ana Klimovic

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and μs-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present ix, a dataplane operating system ...

Association for Computing Machinery2016

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Miguel Sérgio De Oliveira Branco, Pinar Tözün, Danica Porobic, Ippokratis Pandis

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

A Bio-Inspired Reconfigurable Architecture for Local Binary Descriptors

Selman Ergünay, Yusuf Leblebici

Limited resources of embedded devices and increased real time constraints have raised interest to the binary description methods over the floating-point ones such as SIFT and SURF in computer vision applications. Although many software applications of the ...

Ieee2016

Scaling Up Concurrent Analytical Workloads on Multi-Core Servers

Iraklis Psaroudakis

Today, an ever-increasing number of researchers, businesses, and data scientists collect and analyze massive amounts of data in database systems. The database system needs to process the resulting highly concurrent analytical workloads by exploiting modern ...

EPFL2016