Publications associées à Puce d'accélération de réseaux de neurones

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

Bridging Monte Carlo worlds: a new framework for accelerator simulations applied on shielding and machine protection studies

André Donadon Servelle

This thesis delves into the critical study of particle transport in matter, particularly emphasising its implications for machine protection at CERN's accelerator complex and facilities. To conduct studies of this nature, FLUKA and Geant4 stand out within ...

EPFL2024

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Anastasia Ailamaki, Viktor Sanca

Modern data management systems aim to provide both cutting-edge functionality and hardware efficiency. With the advent of AI-driven data processing and the post-Moore Law era, traditional memory-bound scale-up data management operations face scalability ch ...

2023

Hardware-Software Co-design for Improved Resource Utilization in DNN Accelerators

Ahmet Caner Yüzügüler

Deep neural networks (DNN) have become an essential tool to tackle challenging tasks in many fields of computer science. However, their high computational complexity limits their applicability. Specialized DNN accelerators have been developed to accommodat ...

EPFL2023

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Andreea Nica

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

Real-Time Localization for Closed-Loop Control of Assistive Furniture

Auke Ijspeert, Alexandre Massoud Alahi, Lixuan Tang, Anastasia Bolotnikova, George Adaimi, Chuanfang Ning

For people with limited mobility, navigating in cluttered indoor environment is challenging. In this work, we propose a mobile assistive furniture suite that is designed to ease the life of people with special needs in indoor movement. To enable intelligen ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Active Wire Fences for Multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Stasa Kostic, Andela Kostic

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

2023

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

Felix Schürmann, Pramod Shivaji Kumbhar, Omar Awile, Snehal Pramod Kumbhar, Ioannis Magkanaris

Advances in computational capabilities and large volumes of experimental data have established computer simulations of brain tissue models as an important pillar in modern neuroscience. Alongside, a variety of domain specific languages (DSLs) have been dev ...

ACM2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

ASSOC COMPUTING MACHINERY2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

System Support for Robust Distributed Learning

Arsany Hany Abdelmessih Guirguis

Machine learning (ML) applications are ubiquitous. They run in different environments such as datacenters, the cloud, and even on edge devices. Despite where they run, distributing ML training seems the only way to attain scalable, high-quality learning. B ...

EPFL2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

In-Memory Hardware and Architectural Extensions for Workloads Acceleration

William Andrew Simon

Utilization of edge devices has exploded in the last decade, with such use cases as wearable devices, autonomous driving, and smart homes. As their ubiquity grows, so do expectations of their capabilities. Simultaneously, their formfactor and use cases lim ...

EPFL2022