Scratchpad memory

Applied sciences
Génie informatique
Calcul intensif
Parallélisme (informatique)

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Publications associées (29)

Trace-based manycore partitioning of stream-processing applications

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

Application performance on these processor array platforms is highly sensitive to how functionality is physically placed on the device, as this choice crucially determines communication latencies and congestion patterns of the on-chip inter-core communicat ...

2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Miguel Sérgio De Oliveira Branco, Pinar Tözün, Danica Porobic, Ippokratis Pandis

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

Scale-out non-uniform memory access

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memor ...

2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

OCEAN: An Optimized HW/SW Reliability Mitigation Approach for Scratchpad Memories in Real-Time SoCs

David Atienza Alonso, Mohamed Mostafa Sabry Aly

Recent process technology advances trigger reliability issues that degrade the Quality-of-Service (QoS) required by embedded Systems-on-Chip (SoCs). To maintain the required QoS with acceptable overheads, we propose OCEAN, a novel cross-layer error mitigat ...

ACM2014

ATraPos: Adaptive Transaction Processing on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Erietta Liarou

Nowadays, high-performance transaction processing applications increasingly run on multisocket multicore servers. Such architectures exhibit non-uniform memory access latency as well as non-uniform thread communication costs. Unfortunately, traditional sha ...

2014

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

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