Publications associées à Executable and Linkable Format

An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing

David Atienza Alonso, Giovanni Ansaloni, José Angel Miranda Calero, Juan Pablo Sapriza Araujo, Rubén Rodríguez Álvarez, Benoît Walter Denkinger, Ruben Rodriguez

In this work, we propose an open-hardware low-power coarse-grained reconfigurable array connected to a lightweight microcontroller and enclosed in an application mapping framework. The latter provides complete support to configure kernels in the reconfigur ...

2023

Broadening artificial intelligence education in K-12: Where to Start?

Pierre Dillenbourg

Moving from steam and waterpower, electricity and assembly lines, and computerization, to the adoption of cyber-physical systems, the Internet of Things and the Internet of Systems executed as intelligent machines, the world now dives into a new era called ...

2020

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

IEEE2020

HALucinator: Firmware Re-hosting Through Abstraction Layer Emulation

Mathias Josef Payer

Given the increasing ubiquity of online embedded devices, analyzing their firmware is important to security, privacy, and safety. The tight coupling between hardware and firmware and the diversity found in embedded systems makes it hard to perform dynamic ...

USENIX ASSOC2020

RetroWrite: Statically Instrumenting COTS Binaries for Fuzzing and Sanitization

Mathias Josef Payer, Duo Xu

Analyzing the security of closed source binaries is currently impractical for end-users, or even developers who rely on third-party libraries. Such analysis relies on automatic vulnerability discovery techniques, most notably fuzzing with sanitizers enable ...

IEEE COMPUTER SOC2020

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Soumya Subhra Basu, Loris Gérard Duch

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, than ...

2019

Reconciling Being in-Control vs. Being Helped for the Execution of Complex Movements in VR

Ronan Boulic, Bruno Herbelin, Thibault Serge Mario Porssut

Performing motor tasks in virtual environments is best achieved with motion capture and animation of a 3D character that participants control in real time and perceive as being their avatar in the virtual environment. A strong Sense of Embodiment (SoE) for ...

IEEE2019

Data To Reproduce "Cim-Citysim Coupling" On The Epfl Campus

Jean-Louis Scartezzini, Dasaraden Mauree, Silvia Coccolo

The data to reproduce results from the paper " Multi-scale modelling to evaluate building energy consumption at the neighbourhood scale " with DOI : 10.1371/journal.pone.0183437 can be found in this repository. We provide the useful data to rerun the CityS ...

2017

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Ivan Beretta

Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabiliti ...

IEEE/ACM Press2014

Deprogramming Large Software Systems

George Candea, Yohann Coppel

Developers turn ideas, designs and patterns into source code, then compile the source code into executables. Decompiling turns executables back into source code, and deprogramming turns code back into designs and patterns. In this paper we introduce DeP, a ...

2008

The DISCOVER codec: Architecture, Techniques and Evaluation

Mourad Ouaret

Distributed Video Coding is becoming more and more popular among the research community, because of its interesting theoretical contributions and because there are still many open problems waiting to be solved. This paper introduces the codec architecture ...

2007

A Method of Functional Alignment Verification in Hierarchical Enterprise Models

Alain Wegmann, Irina Rychkova

Enterprise modeling involves multiple domains of expertise: requirements engineering, business process modeling, IT development etc. Our experience has shown that hierarchical enterprise models, made of an assembly of system models, are effective. In these ...

2006

A Quantitative Evaluation of the Contribution of Native Code to Java Workloads

Philippe Moret

Many performance analysis tools for Java focus on tracking executed bytecodes, but provide little support in determining the specific contribution of native code libraries. This paper introduces and assesses a portable approach for characterizing the amoun ...

2006

A Complete Network-On-Chip Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Roman Hermida Correa, Nicolas Genko

Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular ...

2005

The TopModL Initiative

Frédéric Fondement

We believe that there is a very strong need for an environment to support research and experiments on model-driven engineering. Therefore we have started the TopModL project, an open-source initiative, with the goal of building a development community to p ...

2005

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

Giovanni De Micheli, David Atienza Alonso, Nicolas Genko

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular ...

2005

Generation of object-oriented programs from CO-OPN specifications

Stanislav Chachkov

The execution of formal specifications is important for verification, validation and animation purposes. This thesis describes transformation of CO-OPN specifications in executable code. The original goal of this transformation was validation by prototypin ...

EPFL2004