Publications de Luca Benini | EPFL Graph Search

Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters

Institute of Electrical and Electronics Engineers (IEEE)2024

Modular Design and Optimization of Biomedical Applications for Ultra-Low Power Heterogeneous Platforms

David Atienza Alonso, Luca Benini, Benoît Walter Denkinger, Elisabetta De Giovanni, Miguel Peon Quiros, Fabio Montagna, Simone Machetti

In the last years, remote health monitoring is becoming an essential branch of health care with the rapid development of wearable sensors technology. To meet the demand of new more complex applications and ensuring adequate battery lifetime, wearable senso ...

2020

Energy Proportionality in Near-Threshold Computing Servers and Cloud Data Centers: Consolidating or Not?

David Atienza Alonso, Luca Benini, Ali Pahlevan, Marina Zapater Sancho, Yasir Mahmood Qureshi

Cloud Computing aims to efficiently tackle the increasing demand of computing resources, and its popularity has led to a dramatic increase in the number of computing servers and data centers worldwide. However, as effect of post-Dennard scaling, computing ...

2018

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

David Atienza Alonso, Luca Benini, Ruben Braojos Lopez, Giovanni Ansaloni

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiog ...

Institute of Electrical and Electronics Engineers2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Luca Benini, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Adam Shmuel Teman

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million o ...

Institute of Electrical and Electronics Engineers2017

Networks on Chips: 15 Years Later

Giovanni De Micheli, Luca Benini

The authors of a Computer article from 2002 reflect on their proposal to use networks on chips to address scalable communications on silicon VLSI chips. ...

2017

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Luca Benini, Aya Mohamed Naguib Ahmed Ibrahim, Marcel Arditi

Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg, Adam Shmuel Teman

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Towards Near-Threshold Server Processors

David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, Babak Falsafi, Javier Picorel Obando, Ali Pahlevan, Arash Pourhabibi Zarandi, Marina Zapater Sancho

The popularity of cloud computing has led to a dramatic increase in the number of data centers in the world. The ever-increasing computational demands along with the slowdown in technology scaling has ushered an era of power-limited servers. Techniques suc ...

IEEE/ACM2016

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging

Giovanni De Micheli, Federico Angiolini, Luca Benini, Aya Mohamed Naguib Ahmed Ibrahim, Marcel Arditi

3D ultrasound imaging is quickly becoming a refer- ence technique for high-quality, accurate, expressive diagnostic medical imaging. Unfortunately, its computation requirements are huge and, today, demand expensive, power-hungry, bulky processing resources ...

IEEE2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

Pierre Vandergheynst, David Atienza Alonso, Luca Benini, Hossein Mamaghanian

Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. Energy consumption severely limits such applications and memories are becoming the energy bottleneck to achieve ultra- ...

IEEE/ACM Press2014

Peak Shift Measurement of Localized Surface Plasmon Resonance by a Portable Electronic System

Luca Benini, Enrico Accastelli, Carlotta Guiducci, Giulia Cappi

In recent years, the characterization of surface molecular layers by localized surface plasmon resonance (LSPR) has attracted a lot of interest thanks to its ability to provide a higher spatial resolution with respect to standard SPR. LSPR can be observed ...

Elsevier2013

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu, Dara Rahmati, Hamid Sarbazi-Azad

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

Assoc Computing Machinery2013

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

This paper introduces SIMinG-1k-a manycore simulator infrastructure. SIMinG-1k is a graphics processing unit accelerated, parallel simulator for design-space exploration of large-scale manycore systems. It features an optimal trade-off between modeling acc ...

Wiley-Blackwell2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Giovanni De Micheli, Federico Angiolini, Luca Benini, Srinivasan Murali, Dara Rahmati, Hamid Sarbazi-Azad

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

Institute of Electrical and Electronics Engineers2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Giovanni De Micheli, Federico Angiolini, Luca Benini, Jaime Joven Murillo

Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded pla ...

Elsevier2013

Full System Simulation of Many-Core Heterogeneous SoCs using GPU and QEMU Semihosting

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Modern system-on-chips are evolving towards complex and heterogeneous platforms with general-purpose processors coupled with massively parallel manycore accelerator fabrics (e.g. embedded GPUs). Platform developers are looking for efficient full-system sim ...

2012