Publications de Ciprian Seiculescu

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu, Dara Rahmati, Hamid Sarbazi-Azad

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

Assoc Computing Machinery2013

3.5-D Integration: A Case Study

Giovanni De Micheli, Ciprian Seiculescu, Shashi Kanth Bobba, Vasileios Pavlidis, Pierre-Emmanuel Julien Marc Gaillardon

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Giovanni De Micheli, Luca Benini, Ciprian Seiculescu

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

Giovanni De Micheli, Ciprian Seiculescu, Babak Falsafi, Naser Khosro Pour, Stavros Volos, Boris Robert Grot

Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...

2012

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

Ciprian Seiculescu

As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor ...

EPFL2012

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the applicat ...

2010

Networks on Chips: From Research to Products

Giovanni De Micheli, Federico Angiolini, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

2010

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

2009

Synthesis of Networks on Chips for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

2009

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

2009