Publications de José Luis Ayala Rodrigo

HackRF plus GNU Radio: A software-defined radio to teach communication theory

José Luis Ayala Rodrigo, Roman Hermida Correa, Marina Zapater Sancho

In this paper, an alternative to the traditional methodology related to signal processing-like subjects is proposed. These are subjects that require a deep mathematical and theoretical basis, but the practical goal is not often emphasized, which drives stu ...

SAGE PUBLICATIONS LTD2019

Fast Energy Estimation Through Partial Execution of HPC Applications

José Luis Ayala Rodrigo, Marina Zapater Sancho

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via d ...

IEEE2018

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to cons ...

IEEE Press2011

Through Silicon Via-Based Grid for Thermal Control in 3D Chips

Yusuf Leblebici, David Atienza Alonso, Vinod Pangracious, José Luis Ayala Rodrigo, Arvind Raj Mahankali Sridhar

3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communica ...

Springer2009

Dynamic Thermal Management in 3D Multicore Architectures

Yusuf Leblebici, David Atienza Alonso, Ayse Kivilcim Coskun, José Luis Ayala Rodrigo

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and dela ...

IEEE and ACM2009

Modeling and Dynamic Management of 3D Multicore Systems with Liquid Cooling

David Atienza Alonso, Ayse Kivilcim Coskun, José Luis Ayala Rodrigo

Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, and coolin ...

IEEE/IFIP Press2009

Thermal-Aware Data Flow Analysis

David Atienza Alonso, Philip Brisk, José Luis Ayala Rodrigo

IEEE Press2009

Joint Hardware-Software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this ...

2008

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

David Atienza Alonso, Pablo Garcia del Valle, José Luis Ayala Rodrigo

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be ...

IEEE Computer Society2008

Reliability-Aware Design for Nanometer-Scale Devices

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, José Luis Ayala Rodrigo

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expecte ...

2008

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

David Atienza Alonso, José Luis Ayala Rodrigo

This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer: layout topology, plac ...

IEEE Computer Society2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...

2007