Publications de Luca Gaetano Amarù

LUT-Based Optimization For ASIC Design Flow

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

2021

SAT-Sweeping Enhanced for Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesis appl ...

IEEE2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa, Mathias Soeken, Heinz Riener

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

IEEE2020

Extending Boolean Methods for Scalable Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Eleonora Testa, Mathias Soeken

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

2020

Logic Optimization of Majority-Inverter Graphs

Giovanni De Micheli, Luca Gaetano Amarù, Winston Jason Haaswijk, Eleonora Testa, Mathias Soeken, Heinz Riener

Majority-inverter graphs (MIGs) are a multi-level logic representation of Boolean functions with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of conventional logic representations. In this pa ...

VDE Verlag2019

Scalable Boolean Methods in a Modern Synthesis Flow

Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Jingshan Luo, Eleonora Testa, Mathias Soeken

With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher computational cost ...

2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All

Giovanni De Michele, Luca Gaetano Amarù, Winston Jason Haaswijk, Eleonora Testa, Mathias Soeken, Heinz Riener

ACM2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa, Mathias Soeken

Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our appro ...

ASSOC COMPUTING MACHINERY2019

Mapping Monotone Boolean Functions into Majority

Giovanni De Micheli, Luca Gaetano Amarù, Winston Jason Haaswijk, Eleonora Testa, Mathias Soeken

We consider the problem of decomposing monotone Boolean functions into majority-of-three operations, with a particular focus on decomposing the majority-n function. When targeting monotone Boolean functions, Shannon's expansion can be expressed by a single ...

2018

Logic Synthesis for Established and Emerging Computing

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa, Mathias Soeken

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has ...

2018

Improvements to Boolean resynthesis

Giovanni De Micheli, Luca Gaetano Amarù, Mathias Soeken

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa, Mathias Soeken, Heinz Riener

Majority-inverter graphs (MIGs) are a logic representation with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of traditional logic representations. Further, since many nano-emerging technologi ...

ASSOC COMPUTING MACHINERY2018

Practical Exact Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Winston Jason Haaswijk, Eleonora Testa, Mathias Soeken

In this paper, we discuss recent advances in exact synthesis, considering both their efficient implementation and various applications in which they can he employed. We emphasize on solving exact synthesis through Boolean satisfiability (SAT) encodings. Di ...

IEEE2018

Canonical Computation without Canonical Representation

Ana Petkovska, Luca Gaetano Amarù, Mathias Soeken

A representation of a Boolean function is canonical if, given a variable order, only one instance of the representation is possible for the function. A computation is canonical if the result depends only on the Boolean function and a variable order, and do ...

IEEE2018

Majority Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Odysseas Zografos, Eleonora Testa, Mathias Soeken

The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...

ASSOC COMPUTING MACHINERY2018

Integrated ESOP Refactoring for Industrial Designs

Giovanni De Micheli, Luca Gaetano Amarù, Winston Jason Haaswijk, Mathias Soeken

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operat ...

IEEE2018

Enabling exact delay synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken

Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the output(s). The exact ...

IEEE2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Paolo Ienne, Giovanni De Micheli, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Zhufei Chu

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

ACM2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken

We propose effective algorithms for exact synthesis of Boolean logic networks using satisfiability modulo theories (SMT) solvers. Since exact synthesis is a difficult problem, it can only be applied efficiently to very small functions, having up to 6 varia ...

Ieee-Inst Electrical Electronics Engineers Inc2017

A Novel Basis for Logic Rewriting

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Winston Jason Haaswijk, Mathias Soeken

Given a set of logic primitives and a Boolean function, exact synthesis finds the optimum representation (e.g., depth or size) of the function in terms of the primitives. Due to its high computational complexity, the use of exact synthesis is limite ...

Ieee2017