Publications de Ali Saeidi | EPFL Graph Search

Ultra-High Sensitivity Silicon Nanowire Array Biosensor Based on a Constant-Current Method for Continuous Real-Time pH and Protein Monitoring in Interstitial Fluid

Mihai Adrian Ionescu, Yann Christophe Sprunger, Ali Saeidi, Luca Capua

In this paper we demonstrate ultra-high sensitivity silicon nanowires pH and protein sensing on the same Silicon nanowire array platform by using a constant current method and monitoring the drain voltage as function of analyte concentration. The injected ...

IEEE2023

Ferroelectric Junctionless Double-Gate Silicon-On-Insulator FET as a Tripartite Synapse

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Matteo Cavalieri, Carlotta Gastaldi, Sadegh Kamaei Bahmaei

In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-termina ...

Institute of Electrical and Electronics Engineers2023

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Mihai Adrian Ionescu, Jürgen Brugger, Ali Saeidi, Carlotta Gastaldi, Sadegh Kamaei Bahmaei, Xia Liu

The co-integration of logic switches and neuromorphic functions could be used to create new computing architectures with low power consumption and novel functionalities. Two-dimensional (2D) semiconductors and ferroelectric materials could be potentially u ...

NATURE PORTFOLIO2023

Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Francesco Bellando, Matteo Cavalieri, Eamon Patrick O'Connor, Carlotta Gastaldi

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond- ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Fully integrated Si:HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs

Mihai Adrian Ionescu, Jürgen Brugger, Clara-Fausta Moldovan, Ali Saeidi, Carlotta Gastaldi, Sadegh Kamaei Bahmaei, Xia Liu

We report the first experimental demonstration and performance characterization of a fully integrated negative capacitance (NC) WSe2/SnSe2 p-type Tunnel FETs (TFETs), validating the use of NC as a technology booster to achieve a significantly improved sub- ...

IEEE2022

Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Igor Stolichnov, Mihai Adrian Ionescu, Teodor Rosca, Ali Saeidi, Matteo Cavalieri, Eamon Patrick O'Connor, Carlotta Gastaldi, Sadegh Kamaei Bahmaei

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applicati ...

AMER INST PHYSICS2021

Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

Mihai Adrian Ionescu, Teodor Rosca, Ali Saeidi, Matteo Cavalieri, Luca Capua, Carlotta Gastaldi, Sadegh Kamaei Bahmaei

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a ...

NATURE PORTFOLIO2021

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Igor Stolichnov, Mihai Adrian Ionescu, Teodor Rosca, Ali Saeidi, Matteo Cavalieri

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

AMER CHEMICAL SOC2020

An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction

Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi, Nicolò Oliva, Benjamin Paul Johanès Gabriel Lambert, Matteo Cavalieri, Sadegh Kamaei Bahmaei, Amin Rassekh

This experimental study investigates a novel multi-functional one dimensional-two dimensional (1D-2D) heterojunction made of two different band-gap semiconductors, i.e. single-walled carbon nanotube (SWCNT) and tungsten di-selenide (WSe2). The proposed ult ...

Institute of Electrical and Electronics Engineers2020

Subthermionic negative capacitance ion sensitive field-effect transistor

Mihai Adrian Ionescu, Ali Saeidi, Francesco Bellando, Carlotta Gastaldi

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for th ...

2020

Negative capacitance semiconductor sensor

Mihai Adrian Ionescu, Ali Saeidi, Francesco Bellando

The present invention relates to a semiconductor sensor (1) comprising: a source element (17, 19); a drain element (21, 23); a semiconductor channel element (25) between the source element (17, 19) and the drain element (21, 23) for forming an electrically ...

2020

Corrections to “Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization”

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Hiroshi Iwai

This correspondence highlights that the Gibbs free energy description of a ferroelectric capacitor in series with a paraelectric capacitor, depends on the initial charge on the plates of the ferroelectric capacitor. An incomplete Gibbs free energy descript ...

2020

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Transient Negative Capacitance of Silicon-doped HfO2 in MFMIS and MFIS structures: experimental insights for hysteresis-free steep slope NC FETs

Paul Muralt, Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Matteo Cavalieri, Carlotta Gastaldi

In this paper, we experimentally explore the transient negative capacitance effect in ferroelectric high-k gate stacks using multi-ferroelectric domain Si-doped HfO2 with and without the metal plane, MFMIS (TiN/Si:HfO2/TiN/SiO2) and MFIS (TiN/Si:HfO2/SiO2) ...

IEEE2019

Near Hysteresis-Free Negative Capacitance InGaAs Tunnel FETs with Enhanced Digital and Analog Figures of Merit below VDD=400mV

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Hiroshi Iwai

We report the universal boosting impact of a true negative capacitance (NC) effect on digital and analog performances of Tunnel FETs (TFETs), mirrored for the first time in near hysteresis-free experiments and exploiting the S-shaped polarization character ...

2019

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a ...

2018

Charge-based Model for Junction FETs

Jean-Michel Sallese, Ali Saeidi

2018

Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs

Christian Enz, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Impact of physical parameters of ferroelectric layer on the performance of Negative Capacitance (NC) MOSFETs is experimentally studied in this paper. Electrical behaviors of PZT-based and Si:HfO2-based NC-FETs are investigated and discussed. In a PZT-based ...

2018

Near Hysteresis-Free Negative Capacitance InGaAs Tunnel FETs with Enhanced Digital and Analog Figures of Merit below V-DD=400mV

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Hiroshi Iwai

We report the universal boosting impact of a true negative capacitance (NC) effect on digital and analog performances of Tunnel FETs (TFETs), mirrored for the first time in near hysteresis-free experiments and exploiting the S-shaped polarization character ...

IEEE2018