Publications associées à Virtual Capacitor Concept for Computationally Efficient and Flexible Real-Time MMC Model

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Andreea Nica

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Anastasia Ailamaki, Viktor Sanca

Modern data management systems aim to provide both cutting-edge functionality and hardware efficiency. With the advent of AI-driven data processing and the post-Moore Law era, traditional memory-bound scale-up data management operations face scalability ch ...

2023

Virtual Capacitor Concept for Partitioning of Large Converter Systems for RT-HIL Simulations

Philippe Alexandre Bontemps, Drazen Dujic, Stefan Milovanovic

In this paper, the real-time simulation model of the modular multilevel matrix converter was split into three independent instances using the concept of virtual capacitance. In doing so, the number of state space matrices that define the system has been re ...

2022

Virtual Capacitor Concept for Effective Real-Time MMC Simulations

Drazen Dujic, Min Luo, Stefan Milovanovic

In this paper, the real-time simulation model of the modular multilevel converter was split into several independent parts through the use of the virtual capacitor concept. As a result, the number of state-space matrices the real-time solver needs to take ...

2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Momentum space CFT correlators for Hamiltonian truncation

Matthew Thomas Walters

We consider Lorentzian CFT Wightman functions in momentum space. In particular, we derive a set of reference formulas for computing two- and three-point functions, restricting our attention to three-point functions where the middle operator (corresponding ...

Springer Nature2020

Beyond Cameras: Real-Time High-Resolution 3D and Panoramic MultiView Vision Systems with Their Applications

Bilal Demir

The cameras are invented by imitating the human visual system to capture the scene. The camera technologies have been substantially advanced in recent years. 108 MP resolution with 100x hybrid zoom has become standard features for smartphone flagships. In ...

EPFL2020

Kinetic Euclidean Distance Matrices

Martin Vetterli, Ivan Dokmanic, Puoya Tabaghi

Euclidean distance matrices (EDMs) are a major tool for localization from distances, with applications ranging from protein structure determination to global positioning and manifold learning. They are, however, static objects which serve to localize point ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems

Yusuf Leblebici, Severin Sidler, Alessandro Fumarola

Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, ...

IEEE2019

Computational characteristics and hardware implications of brain tissue simulations

Francesco Cremonesi

Understanding the link between the brain's anatomy and its function through computer simulations of neural tissue models is a widely used approach in computational neuroscience. This technique enables rapid prototyping and testing of hypotheses, allowing r ...

EPFL2019

New Approach to Identifying Critical Initial Conditions for Extreme Flood Simulations in a Semicontinuous Simulation Framework

Bettina Schaefli, Anton Schleiss, Javier García Hernández, Fränz Zeimetz, Guillaume Mathieu Artigue

Extreme flood simulation with synthetic extreme precipitation events raises unavoidable questions about the choice of initial conditions. State-of-the-art extreme flood estimation frameworks propose to address these questions with the help of semicontinuou ...

2018