Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

À propos
Confidentialité
Mentions légales

Graph Chatbot

Publications associées (30)

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato, Kiarash Gharibdoust

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

Elsevier2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for ...

2016

High-level system synthesis and optimization of dataflow programs for MPSoCs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level o ...

2016

Hardware/Software Co-Design of Ultra-Low Power Biomedical Monitors

Ruben Braojos Lopez

Ongoing changes in world demographics and the prevalence of unhealthy lifestyles are imposing a paradigm shift in healthcare delivery. Nowadays, chronic ailments such as cardiovascular diseases, hypertension and diabetes, represent the most common causes o ...

EPFL2016

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration

Endri Bezati

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for comp ...

EPFL2015

System Design Automation: Challenges and Limitations

Joseph Sifakis

Electronic design automation (EDA) has enabled the integrated circuit industry to sustain exponentially increasing product complexity growth until today, while maintaining consistent product development timeline and costs. We argue that the success of EDA- ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Page 2 sur 2