Publications associées à Analyzing and comparing the AES architectures for their power consumption

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

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X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

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Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

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Since the advent of internet and mass communication, two public-key cryptographic algorithms have shared the monopoly of data encryption and authentication: Diffie-Hellman and RSA. However, in the last few years, progress made in quantum physics -- and mo ...

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Advanced Silicon and SWIR Single-Photon Avalanche Diodes: Design, Simulation, and Characterization

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Low-level light detection with high spatial and timing accuracy is a growing area of interest by virtue of applications such as light detection and ranging (LiDAR), biomedical imaging, time-resolved Raman spectroscopy, and quantum applications. Single-phot ...

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Highly Parallel RTL Simulation

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EdgeAI-Aware Design of In-Memory Computing Architectures

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Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

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The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

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A Visionary Look at the Security of Reconfigurable Cloud Computing

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Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

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Automating the Design of Programmable Interconnect for Reconfigurable Architectures

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With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

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Active Wire Fences for Multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Andela Kostic, Stasa Kostic

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

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The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

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Recently, we published an article [1] presenting how the Power Electronics course at the bachelor level is organized by the Power Electronics Laboratory and taught at Ecole Polytechnique Fédérale de Lausanne, EPFL, Switzerland. For those avid readers who m ...

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Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

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To answer the growing demand for hardware acceleration, Amazon, Microsoft, and many other major cloud service providers have included field-programmable gate arrays (FPGAs) in their datacenters. However, researchers have shown that cloud FPGAs, when shared ...

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

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Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

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Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

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The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

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Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

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Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

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PAE: Towards More Efficient and BBB-Secure AE from a Single Public Permutation

Ritam Bhaumik

Four recent trends have emerged in the evolution of authenticated encryption schemes: (1) Regarding simplicity, the adoption of public permutations as primitives allows for sparing a key schedule and the need for storing round keys; (2) using the sums of p ...

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IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

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The Side-channel Metrics Cheat Sheet

Francesco Regazzoni, Mirjana Stojilovic, Dorian Ros, Ognjen Glamocanin

Side-channel attacks exploit a physical observable originating from a cryptographic device in order to extract its secrets. Many practically relevant advances in the field of side-channel analysis relate to security evaluations of cryptographic functions a ...

2023