Publications associées à A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

Integrated Wireless Power, Data Communication, and Thermal Sensing System for Autonomous Multisite Brain Implants

Implanted medical devices (IMDs) have been widely developed to support the monitoring and recording of biological data inside the body or brain. Wirelessly powered IMDs, a subset of implantable electronics, have been proposed to eliminate the limitations r ...

EPFL2024

Computational Imaging SPAD Cameras

Andrei Ardelean

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

EPFL2023

Electronic readout of DNA amplification in nanoliter chambers. Strategies towards highly parallel semiconductor-based nucleic acid amplification testing

Saurabh Tomar

Polymerase chain reaction (PCR) has been the most significant driver in the field of nucleic acid testing (NAT) since its invention. Popularized as an abbreviation by the Covid-19 pandemic, PCR-based methods are the gold standard in the field of diagnostic ...

EPFL2023

Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

Jean-Michel Sallese, Adil Koukab, Stefano Michelis, Gennaro Termo

The discovery of a large fab-to-fab variability in the TID response of the CMOS technologies used in the design of ASICs for the particle detectors of the HL-LHC triggered a monitoring effort to verify the consistency of the CMOS production process over ti ...

IOP Publishing Ltd2023

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

High-Performance CMOS SPAD-Based Sensors for Time-of-Flight PET Applications

Francesco Gramuglia

Detecting light, photon by photon, has been possible since the 1930s, with the invention of the photomultiplier tube (PMT). However, it is only since the 1970s, that solid-state single-photon detectors have emerged and only since 2003 that a new technology ...

EPFL2022

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Claudio Bruschini, Edoardo Charbon, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Resource Trade-Offs in Circuits and Systems: from Neurotechnology to Communications

Arda Uran

This thesis aims to explore and exploit trade-offs in integrated circuits and systems to overcome the fundamental bottlenecks faced by future data acquisition and communication systems. Specifically, we target the emerging implantable neurotechnology and t ...

EPFL2021

Exploring ferroelectricity in HfO2-based thin films by tackling application-relevant challenges

Matteo Cavalieri

Ferroelectric materials offer a broad range of application-relevant properties, including spontaneous polarization switchable by electric field. Archetypical representatives of this class of materials are perovskites, currently used in applications ranging ...

EPFL2021

Cryogenic CMOS Integrated Circuits for Scalable Readout of Silicon Quantum Computers

Andrea Ruffino

Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the q ...

EPFL2021

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Odysseas Zografos, Eleonora Testa, Mathias Soeken

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

2020

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Yusuf Leblebici, Gain Kim, Thomas Toifl

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

IEEE2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Yusuf Leblebici, Thomas La Grange, Elmira Shahrabi, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Fabio Sebastiano, Andrea Ruffino, Yatao Peng

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019