Publications associées à DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Is the powersave governor really saving power?

David Atienza Alonso, Luis Maria Costero Valero, Darong Huang

A frequency scaling governor is critical for the performance management of cloud servers, as it enhances energy efficiency and helps to control operational temperatures, thereby ensuring system reliability. However, our in-depth analysis of the application ...

2024

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Claudio Bruschini, Edoardo Charbon, Andrada Alexandra Muntean, Emanuele Ripiccini

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Oligolithic Cross-task Optimizations across Isolated Workloads

Anastasia Ailamaki, Panagiotis Sioulas, Eleni Zapridou

Enterprises collect data in large volumes and leverage them to drive numerous concurrent decisions and business processes. Their teams deploy multiple applications that often operate concurrently on the same data and infrastructure but have widely differen ...

2024

Integrated Wireless Power, Data Communication, and Thermal Sensing System for Autonomous Multisite Brain Implants

Implanted medical devices (IMDs) have been widely developed to support the monitoring and recording of biological data inside the body or brain. Wirelessly powered IMDs, a subset of implantable electronics, have been proposed to eliminate the limitations r ...

EPFL2024

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Mathias Josef Payer, Shashwat Shrivastava, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Alexandre Schmid, Keyvan Farhang Razi

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-powe ...

IEEE2023

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Andreea Nica

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Green Cryptography and Other Optimisations

Andrea Felice Caforio

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

Imprecise Store Exceptions

Babak Falsafi, Siddharth Gupta, Mathias Josef Payer, Yunho Oh, Yuanlong Li, Qingxuan Kang, Abhishek Bhattacharjee

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

Naci Pekçokgüler

The crowdedness of the RF spectrum constitutes problems in communication, however it also accommodates large amount of useful information. This information can be used to determine existing signals and operating contexts. However, spectrum condition varies ...

EPFL2024

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023