Publications associées à Timing-Error-Tolerant Network-on-Chip Design Methodology

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Claudio Bruschini, Edoardo Charbon, Andrada Alexandra Muntean, Emanuele Ripiccini

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system ...

Ieee-Inst Electrical Electronics Engineers Inc2024

An aircraft assembly process formalism and verification method based on semantic modeling and MBSE

Dimitrios Kyritsis, Jinzhi Lu, Xiaochen Zheng

The aircraft assembly system is highly complex involving different stakeholders from multiple domains. The design of such a system requires comprehensive consideration of various industrial scenarios aiming to optimize key performance indicators. Tradition ...

Elsevier Sci Ltd2024

Weak correlations between visual abilities in healthy older adults, despite long-term performance stability

Michael Herzog, Simona Adele Garobbio

Using batteries of visual tests, most studies have found that there are only weak correlations between the performance levels of the tests. Factor analysis has confirmed these results. This means that a participant excelling in one test may rank low in ano ...

2024

Thermal Design of a Medium Voltage Modular Multilevel Converter Cell

Drazen Dujic, Yanick Patrick Frei

This paper presents the cooling concept for a medium voltage modular multilevel converter cell. To optimize power density, the metallic enclosure is used to dissipate the heat generated by semiconductor losses, while maintaining maximum temperatures below ...

New York2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

The Case for Performance Interfaces for Hardware Accelerators

George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer, Jiacheng Ma

While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of ...

2023

Latency Interfaces for Systems Code

Rishabh Ramesh Iyer

This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

EPFL2023

Radiation Hardness of MALTA2, a Monolithic Active Pixel Sensor for Tracking Applications

Edoardo Charbon, Ashish Sharma, Francesco Piro

MALTA is a depleted monolithic active pixel sensor (DMAPS) developed in the Tower Semiconductor 180-nm CMOS imaging process. Monolithic CMOS sensors offer advantages over current hybrid imaging sensors in terms of both increased tracking performance due to ...

Ieee-Inst Electrical Electronics Engineers Inc2023

Beyond worst-case analysis, with or without predictions

Andreas Maggiori

In this thesis we design online combinatorial optimization algorithms for beyond worst-case analysis settings. In the first part, we discuss the online matching problem and prove that, in the edge arrival model, no online algorithm can achieve a competiti ...

EPFL2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Performance Interfaces for Network Functions

George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer

Modern programmers routinely use third-party code, and infrastructure operators deploy software they did not write. This would not be possible without semantic interfaces---documentation, header files, specifications---that succinctly describe what that th ...

USENIX Association2022

Design and Preparation of Sensing Surfaces for Capacitive Biodetection

Sandrine Gerber, Perrine Agnes Edith Robin

Despite their high sensitivity and their suitability for miniaturization, biosensors are still limited for clinical applications due to the lack of reproducibility and specificity of their detection performance. The design and preparation of sensing surfac ...

2023

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Charly Nicolas Lucien Castes

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

IEEE COMPUTER SOC2022

Development of a large-area, light-weight module using the MALTA monolithic pixel detector

Edoardo Charbon, Ashish Sharma, Francesco Piro

The MALTA pixel chip is a 2 cm x 2 cm large monolithic pixel detector developed in the Tower 180 nm imaging process. The chip contains four CMOS transceiver blocks at its sides which allow chip-to-chip data transfer. The power pads are located mainly at th ...

ELSEVIER2022

Cost-Based Decision Support System: A Dynamic Cost Estimation of Key Performance Indicators in Manufacturing

Dimitrios Kyritsis, Foivos Psarommatis Giannakopoulos

An attempt is made to translate five generic key performance indicators (KPIs) into a continuous real-time cost function in a batch order-based manufacturing environment. The challenge of controlling and optimizing resource utilization, production efficien ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Hardware and Software Support for RPC-Centric Server Architecture

Mark Johnathon Sutherland

Online services have become ubiquitous in technological society, the global demand for which has driven enterprises to construct gigantic datacenters that run their software. Such facilities have also recently become a substrate for third-party organizatio ...

EPFL2022

A Noise-Resistant Mixed-Discrete Particle Swarm Optimization Algorithm for the Automatic Design of Robotic Controllers

Alcherio Martinoli, Cyrill Silvan Baumann

The automatic design of well-performing robotic controllers is still an unsolved problem due to the inherently large parameter space and noisy, often hard-to-define performance metrics, especially when sequential tasks need to be accomplished. Distal contr ...

2022

Adaptive Body Biasing in Strong Body Factor Technologies

Thomas Christoph Müller

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy b ...

EPFL2021

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Marcos Vinícius Silva Oliveira

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

EPFL2021

Automated Design: A Journey Across Modelling, Optimization, and Education

Cyril Picard

Machine intelligence greatly impacts almost all domains of our societies. It is profoundly changing the field of mechanical engineering with new technical possibilities and processes. The education of future engineers also needs to adapt in terms of techni ...

EPFL2021