Publication
Semiconductor innovation is shifting from traditional dimensional scaling toward novel architectures and materials as lithography nears its physical limits. FinFETs and GAAFETs have marked key milestones, with scaling now progressing through 3D stacking. Meanwhile, 2D materials like MoS2 offer potential for energy-efficient transistors with increased density. However, beyond-silicon technologies face challenges in industrial integration, primarily due to the lack of CMOS-compatible and scalable fabrication processes for high-yield nanoelectronics and their low electron mobilities (20-30 cm2/V.s), which remain far below the industry target (>100 cm2/V.s).
In this thesis, we explore the third dimension in device architecture through grayscale nanopatterning, enabling engineered surface topographies for the strain engineering of 2D materials. For grayscale nanopatterning, we use thermal scanning probe lithography, which stands out due to its sub-1 nm depth control, but also has inherent challenges, including geometry-dependent spatial resolution, limited patterning depth and aspect ratio, low throughput due to tip scanning, and substrate constraints arising from electrostatic actuation. To expand its potential, we demonstrate: (1) high-aspect-ratio metal tip integration for deeper patterning; (2) grayscale pattern transfer and depth amplification into thin film dielectrics using gentle plasma etching; and (3) scalable replication via nanoimprint lithography with smooth pattern transfer onto various substrates.
We apply these grayscale nanosurfaces to strain-engineer monolayer MoS2 for enhanced electron mobility through two fundamentally distinct approaches: (1) transfer-based strain and (2) transfer-free strained growth. In the transfer-based approach, we achieved electron mobilities up to 185 cm2/V.s (~8x improvement with ~1% tensile strain). However, to eliminate interface issues and contamination caused by polymer-assisted 2D material transfer, we develop a new industry-compatible transfer-free approach: introducing strain in 2D materials during their growth on grayscale-patterned surfaces instead of flat substrates, where the grayscale-thin-film/substrate stack is engineered based on thermal expansion mismatches. This method enables precise control of both strain levels (0-0.5% tensile) through aspect ratio modulation and strain orientations (uniaxial and multiaxial) through topography design, and results in a reproducible and scalable technique that creates contamination-free and air-trap-free semiconductor/dielectric interfaces essential for advanced electronics.
The demonstrated fabrication and strain-engineering techniques present scalable and industry-compatible approaches for realizing high-performance 2D material devices with CMOS integration potential. Moreover, scalable strain engineering in 2D semiconductors holds the potential for both logic device scaling and application innovations in the rapidly growing field of see-through/tran