Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11n standard and achieves a throughput of 780 M bit/s with a core area of 3.39 mm(2) in 0.18 mu m CMOS technology.