Publications related to XNOR gate

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing meets Resynthesis

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window rewriting, repeatedly selects small parts of the logic and replaces them with more compact implem ...

IEEE2022

Highly Sensitive Detection of the Antidepressant Fluoxetine With an Extended Gate Field Effect Transistor

Mihai Adrian Ionescu, Shokoofeh Sheibani

Fluoxetine (FL) is one of the selective serotonin reuptake inhibitors, which is used as an anti-depressant, as well as anti-panic drug. In this work, a sensor for label-free recognition of trace amounts of FL is introduced, which is based on an extended ga ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Further Results on Efficient Implementations of Block Cipher Linear Layers

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Francesco Regazzoni, Subhadeep Banik, Muhammed Fatih Balli, Andrea Felice Caforio

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

IEEE2021

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Heterostructure design and field management in III-N high-electron mobility electronic devices

Catherine Erine

III-N family of materials has offered multiple groundbreaking technologies in the field of optoelectronics and high-power radio-frequency (RF) devices. Blue light-emitting diodes (LEDs) have revolutionized low-energy lighting. Gallium nitride (GaN) RF mark ...

EPFL2021

Wide-field time-gated SPAD imager for phasor-based FLIM applications

Edoardo Charbon, Claudio Bruschini, Ivan Michel Antolovic, Andrei Ardelean, Arin Can Ülkü

We describe the performance of a new wide area time-gated single-photon avalanche diode (SPAD) array for phasor-FLIM, exploring the effect of gate length, gate number and signal intensity on the measured lifetime accuracy and precision. We conclude that th ...

IOP2020

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Hubert Pierre-Marie Benoît Schneegans, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

Logic-in-memory based on an atomically thin semiconductor

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Ahmet Avsar, Yanfei Zhao, Guilherme Migliato Marega, Zhenyu Wang

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

2020

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

Kamiar Aminian, Benedikt Fasel

In alpine skiing, intermediate times are usually measured with photocells. However, for practical reasons, the number of intermediate cells is limited to three⁻four, making a detailed timing analysis difficult. In this paper, we propose and validate a magn ...

2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa

Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our appro ...

ASSOC COMPUTING MACHINERY2019

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

Danick Briand, Herbert Shea, Rubaiyet Iftekharul Haque, Alexis Pierre Henri Marette, Xiaobin Ji, Ronan Julien Hinchet

A high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuat ...

2019

High-performance normally-off tri-gate GaN power MOSFETs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Minghua Zhu

In this work, we present the investigation of the combination of gate recess and tri-gate structures to achieve high performance normally-off GaN-on-Si MOSFETs with high positive threshold voltage ( VTH ), low specific on resistance ( RON,SP ) and high out ...

IEEE2019

Functionality Enhanced Memories for Edge-AI Embedded Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Pierre-Emmanuel Julien Marc Gaillardon, Marco Antonio Rios, William Andrew Simon

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

IEEE2019

On the Dynamic Performance of Laterally Gated Transistors

Elison de Nazareth Matioli, Armin Jafari, Catherine Erine, Giovanni Santoruvo, Mohammad Samizadeh Nikooytabalvandani

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...

Institute of Electrical and Electronics Engineers2019

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

2018

Dynamical Behavior and Stability Analysis of Hydromechanical Gates

Paolo Perona, Fabian Alexander Bernhard

This study revisits the stability of hydromechanical gates for upstream water surface regulation, also known as AMIL gates. AMIL gates are used in irrigation canals, where they are often installed in series. From the regulation perspective, instabilities a ...

American Society of Civil Engineers2017

Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation

Mihai Adrian Ionescu, Christian Enz, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi, Francesco Bellando

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative ca ...

IEEE2017