Publications by Mohamed Haykel Ben Jamaa

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

Institute of Electrical and Electronics Engineers2013

An Efficient Gate Library for Ambipolar CNTFET Logic

Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this ...

2011

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

In this paper, we demonstrate the ability of the multi- spacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize sin ...

Institute of Electrical and Electronics Engineers2011

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

2011

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2010

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Giovanni De Micheli, Mohamed Haykel Ben Jamaa

This paper exploits the unique in-ﬁeld controllability of the device polarity of ambipolar carbon nanotube ﬁeld effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized ...

2009

A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories

Yusuf Leblebici, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correc ...

ACM/IEEE Press2009

Fabrication and design of nanoscale regular circuits

Mohamed Haykel Ben Jamaa

During many decades, Moore's law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry pre ...

EPFL2009

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer ...

2009

Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patt ...

2009

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their org ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 Usa2009

Programmable Logic Circuits based on Ambipolar CNFET

Yusuf Leblebici, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform u ...

2008

Prospects for logic-on-a-wire

Didier Bouvet, Yusuf Leblebici, Mihai Adrian Ionescu, Kirsten Emilie Moselund, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

2008

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Didier Bouvet, Yusuf Leblebici, Mihai Adrian Ionescu, Kirsten Emilie Moselund, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

2008

Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays

Didier Bouvet, Yusuf Leblebici, Mihai Adrian Ionescu, Kirsten Emilie Moselund, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using mu ...

2007

Improving the Fault Tolerance of Nanometric PLA Designs

Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa, Federico Angiolini, Luca Benini

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

2007