Recherche

Afficher tous les résultats pour

Accueil

Personne

Yusuf Leblebici

Cette personne n’est plus à l’EPFL

À propos
Confidentialité
Mentions légales

Graph Chatbot

Publications associées (405)

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Yusuf Leblebici, Thomas La Grange, Elmira Shahrabi, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Yusuf Leblebici, Davide Ceresa, Alessandro Caratelli, Simone Scarfì

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger s ...

IEEE2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Yusuf Leblebici, Seyed Armin Tajalli, Andreas Peter Burg, Ayça Akkaya, Firat Çelik

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems

Yusuf Leblebici, Severin Sidler, Alessandro Fumarola

Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, ...

IEEE2019

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

IEEE2019

Switching Kinetics Control of W-Based ReRAM Cells in Transient Operation by Interface Engineering

Yusuf Leblebici, Thomas La Grange, Mahmoud Hadad, Miguel Ramos, Carlo Ricciardi, Cecilia Giovinazzo

Tungsten (W) is one of the most promising materials to be used in resistive random-access memory electrodes due to its low work function and compatibility with semiconductors, which raises the possibility of device integration, scalability, and low power c ...

WILEY2019

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Yusuf Leblebici, Andreas Peter Burg, Cosimo Aprile, Andrea Bonetti, Nicolas Claude Frigerio, Robert Giterman, Jonathan Emmanuel D Narinx

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

IEEE2019

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Yusuf Leblebici, Gain Kim, Thomas Toifl

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

IEEE2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

IEEE2019

Multi-ReRAM synapses for artificial neural network training

Yusuf Leblebici, Elmira Shahrabi, Irem Boybat Kara, Igor Krawczuk, Abu Sebastian, Carlo Ricciardi, Cecilia Giovinazzo, Evangelos Eleftheriou

Metal-oxide-based resistive memory devices (ReRAM) are being actively researched as synaptic elements of neuromorphic co-processors for training deep neural networks (DNNs). However, device-level non-idealities are posing significant challenges. In this wo ...

IEEE2019

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Yusuf Leblebici, Jury Sandrini, Elmira Shahrabi, Carlo Ricciardi, Cecilia Giovinazzo, Oguz Tolga Celik

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. ...

AMER CHEMICAL SOC2019

Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs

Yusuf Leblebici, Mustafa Kilic, Arda Uran

Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration s ...

IEEE2018

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

2018

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

Catherine Dehollain, Yusuf Leblebici, Volkan Cevher, Mahsa Shoaran, Gürkan Yilmaz, Franco Maloberti, Cosimo Aprile, Kerim Türe, Luca Baldassarre

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we ...

2018

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

2018

Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network Training Accuracy

Yusuf Leblebici, Severin Sidler, Alessandro Fumarola

2018

Page 2 sur 21

Yusuf Leblebici

Graph Chatbot

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Switching Kinetics Control of W-Based ReRAM Cells in Transient Operation by Interface Engineering

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Multi-ReRAM synapses for artificial neural network training

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network Training Accuracy

FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation

Neuromorphic computing with multi-memristive synapses

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI