Publications de Wladyslaw Grabinski

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Matthias Bucher, Christian Enz, François Krummenacher, Christophe Lallement, Jean-Michel Sallese, Eric Vittoz, Wladyslaw Grabinski

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. T ...

IEEE2019

Analog RF and mm-Wave Design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

Christophe Lallement, Jean-Michel Sallese, Wladyslaw Grabinski

The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and ...

IEEE2018

FOSS EKV 2.6 parameter extractor

Jean-Michel Sallese, Wladyslaw Grabinski, Anurag Mangla, Antonios Bazigos, Farzan Jazaeri, Maria-Anna Chalkiadaki

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

Ieee2015

Compact Modeling of Homojunction Tunnel FETs

Mihai Adrian Ionescu, Wladyslaw Grabinski, Luca De Michielis, Nilay Dagtekin, Arnab Biswas, Antonios Bazigos, Cem Alper

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

IEEE2014

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 x 10(19) cm(-3) n-type channel doping, 5-20 nm Si nanowire wi ...

Pergamon-Elsevier Science Ltd2014

Steep slope VO2 switches for wide-band (DC-40 GHz) reconfigurable electronics

Mihai Adrian Ionescu, Wladyslaw Grabinski, Andreas Schueler, Montserrat Fernandez-Bolanos Badia, Antonio Paone, Wolfgang Amadeus Vitale, Antonios Bazigos

IEEE2014

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Mihai Adrian Ionescu, Wladyslaw Grabinski, Nilay Dagtekin, Arnab Biswas, Antonios Bazigos

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices ...

American Institute of Physics2014

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

A study on 1T Capacitor-less Tunnel FET DRAM Exploiting Ungated Body

Mihai Adrian Ionescu, Wladyslaw Grabinski, Nilay Dagtekin, Arnab Biswas, Antonios Bazigos

IEEE2013

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET ...

Institute of Electrical and Electronics Engineers2012

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

Didier Bouvet, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-section cores on bulk Si substrate using optical lithography, hard mask/spacer technology and local oxidation. 0.8 GPa uniax ...

Institute of Electrical and Electronics Engineers2012

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

Elsevier2012

Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Didier Bouvet, Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

Elsevier2012