Michail Zervas

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Publications associées (32)

High throughput screening platform for ultra large scale integration based on high-k silicon nanowire ISFET and 3D integration

Michail Zervas

EPFL2013

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

John Richard Thome, Yusuf Leblebici, Yassir Madhour, Michail Zervas, Bruno Michel

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconn ...

IEEE2013

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Yüksel Temiz, Davide Sacchetto

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching ...

Institute of Electrical and Electronics Engineers2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Panagiotis Athanasopoulos, Michail Zervas, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Yusuf Leblebici, Michail Zervas, Yüksel Temiz, Carlotta Guiducci

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Michail Zervas, Andreea Veronica Savu, Davide Sacchetto, Shenqi Xie

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

Fabrication and characterization of wafer-level deep TSV arrays

Yusuf Leblebici, Michail Zervas, Yüksel Temiz

Three Dimensional (3D) integration, based on through silicon vias (TSV), has the potential to become a key enabling technology for many applications. TSVs are commonly categorized according to their aspect ratio and diameter. An equally important parameter ...

IEEE2012

Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Michail Zervas, Andreea Veronica Savu, Davide Sacchetto, Shenqi Xie

2011

Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

Yusuf Leblebici, Michail Zervas, Yüksel Temiz, Carlotta Guiducci

This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is t ...

2011

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

Elsevier2011

Monolithic Integration of Silicon Nanowires With a Microgripper

Yusuf Leblebici, Michail Zervas, Özgür Özsun, Izzet Yildiz, Mustafa Yilmaz

Si nanowire (NW) stacks are fabricated by utilizing the scalloping effect of inductively coupled plasma deep reactive ion etching. When two etch windows are brought close enough, scallops from both sides will ideally meet along the dividing centerline of t ...

Institute of Electrical and Electronics Engineers2009

On heat transfer at microscale with implications for microactuator design

Yusuf Leblebici, Michail Zervas, Özgür Özsun, Mustafa Yilmaz

The dominance of conduction and the negligible effect of gravity, and hence free convection, are verified in the case of microscale heat sources surrounded by air at atmospheric pressure. A list of temperature-dependent heat transfer coefficients is provid ...

Institute of Physics2009

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