Publications associées à Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Graph generative deep learning models with an application to circuit topologies

Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison. Managing their complexity and facilitating their design drove part of the co-evolution of mode ...

EPFL2024

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Claudio Bruschini, Edoardo Charbon, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Halima Najibi, Giovanni Ansaloni, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

2022

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Halima Najibi

Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) are promising solutions for highly intensive Artificial Intelligence (AI) and Big Data applications. They combine remarkably dense computation capabilities and massive communication bandwidths. ...

EPFL2022

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Harsh Ambarishkumar Shukla

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

EPFL2021

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Halima Najibi, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

David Atienza Alonso, Soumya Subhra Basu, Giovanni Ansaloni, Loris Gérard Duch, Miguel Peon Quiros

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, than ...

2019

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Winston Jason Haaswijk

Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...

EPFL2019

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

An integrative approach for embodied energy: Towards an LCA-based data-driven design method

Emmanuel Rey, Marilyne Andersen, Thomas Bernard Paul Jusselme

The built environment is one of the major contributors of greenhouse gas (GHG) emissions. To tackle climate change, global targets have been set for this sector. Although life-cycle assessment (LCA) methods are typically used to evaluate a building project ...

2018

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

David Atienza Alonso, Ayse Kivilcim Coskun, Artem Andreev, Marina Zapater Sancho, Fulya Kaplan

Integrated flow cell array (FCA) is an emerging technology, targeting the cooling and power delivery challenges of modern 2D/3D Multi-Processor Systems-on-Chip (MPSoCs). In FCA, electrolytic solutions are pumped through microchannels etched in the silicon ...

2018

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Mattia Cacciotti, Jérémy Lucien Maurice Schlachter, Alessandro Pezzotta

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

High level synthesis of Smith-Waterman dataflow implementations

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by wr ...

2017

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg, Adam Shmuel Teman

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Hassan Ghasemzadeh Mohammadi

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

EPFL2016